1. Field of the Invention
The present invention relates to a terminal resistance device, a semiconductor device including the same, and a control method for a terminal resistance.
2. Description of Related Art
Recently, personal computers, servers, work stations and the like have increased in processing speed. In these devices, a signal amplitude which is transmitted between semiconductor devices in such devices becomes smaller so that a delay time for signal transmission is minimized. In the semiconductor devices in which speeding up of processing is required, a technique in which an impedance matching circuit called On Die Termination (ODT) is provided is often used to cut down signal noise and prevent impedance from being unmatched.
FIG. 8 shows a configuration of a terminal resistance device 70 disclosed in FIG. 4 of Japanese Unexamined Patent Application Publication No. 2006-66833. In the Japanese Unexamined Patent Application Publication No. 2006-66833, an LSI 3000 of a transmitting end device provides the terminal resistance device 70 as an interface circuit. The terminal resistance device 70 is configured with a variable terminal resistance unit (ODT circuit) 82 and a terminal resistance control unit (ODT control unit) 83. The variable terminal resistance unit 82 respectively has a plurality of terminal resistance elements 85P and 85N between a transmission path 80 and a source voltage line or a ground voltage line. The terminal resistance elements 85P and 85N are configured with P-type and N-type Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). The P-type transistors of the terminal resistance elements 85P are provided between the transmission path 80 and the source voltage line. The N-type transistors of the terminal resistance elements 85N are provided between the transmission path 80 and the ground voltage line.
The terminal resistance elements 85P and 85N have different resistance values from each other. The resistance values can be adjusted by varying a gate width of the transistor and will be explained using the gate width. For purpose of explanation, gate widths W of terminal resistance elements 85N are represented by W0, W1, W2, and W3 in the order from transistor on the left side in FIG. 8. A ratio of W0:W1:W2:W3 is 1:2:4:8. In the same way, a ratio of the gate widths of the terminal transistor elements 85P is 1:2:4:8 in the order from transistor on the left side in FIG. 8. In the terminal resistance elements 85P and 85N configured as described above, control signals PDRV[0] to [3] and NDRV[0] to [3] transmitted to the gate of each transistor can control connections between the terminal transistor elements 85P and 85N and the transmission path 80.
The terminal resistance control unit 83 includes a logic unit 87, a variable resistance unit 88, and a counter 89. The variable resistance unit 88 provides compare resistance elements (not shown) corresponding to each the terminal resistor elements 85P and 85N of the variable terminal resistance unit 82. Each compare resistance elements is configured such that a plurality of transistors is connectable to a detect point, as in the variable terminal resistance unit 82. Gate of the compare resistance elements receive the control signals which are identical with the control signals PDRV[0] to [3] and NDRV[0] to [3] transmitted to the gates of the terminal resistance elements 85P and 85N. The compare resistance elements are switched to be connected to the detect point by the control signals NDRV and PDRV.
The logic unit 87 sequentially generates code signals based on an output of the counter 89. The logic unit 87 transmits the generated code signals as the control signals PDRV and NDRV to the variable terminal resistance unit 82 and the variable resistance unit 88. The logic unit 87 compares a voltage of the detect point and a reference voltage of a resistance 81, and sets signal states of the control signals PDRV[0] to [3] and NDRV[0] to [3] based on a result of comparison.
FIG. 9 shows changing signal states of the code signals generated in the logic unit 87. The logic unit 87 selects terminal resistance elements 85P and 85N to be connected to the transmission path 80 on the P-type side and N-type side to adjust the terminal resistance. However, for ease of explanation, the case in which the logic unit 87 sets the connection of only the terminal resistance elements 85N of N-type transistors will be described. As described above, the ratio of the gate widths of the terminal resistance elements 85N is W0:W1:W2:W3=1:2:4:8 in the order from the transistor on the left side in FIG. 8.
The logic unit 87 sequentially increments the code signals based on the output of the counter 89. Specifically, in the case where a summation of the gate widths W of the terminal resistance elements 85N, which are connected to the transmission path 80, is set to “0”, the control signals NDRV[0] to [3] are set to “0”. After this manner, all the terminal resistance elements 85N are disconnected from the transmission path 80. In another case where the summation of the gate widths W of the terminal resistance elements 85N, which are connected to the transmission path 80, is set to “1”, only the control signal NDRV[0] transmitted to the terminal resistance element 85N having a gate width W0=1 is set to “1” and the other control signals NDRV[1] to [3] are set to “0”. After this manner, the terminal resistance element 85N having the gate width W0=1 is connected to the transmission path 80.
The summation of the gate widths W of the terminal resistance elements 85N, which are connected to the transmission path 80, becomes larger in accordance with increase of a value of the code signal. A terminal resistance value can be represented as an inverse number of the summation of the gate widths W of the terminal resistance elements 85N connected to the transmission path 80. Accordingly, the terminal resistance value becomes smaller in accordance with increase of the value of the code signal.
Japanese Unexamined Patent Application Publication No. 2008-182516 discloses a device which transmits and receives data through a transmission path. In this device, impedance of a transmitting device side is adjusted using a gate capacitance.